The present inventors have proposed an electronic circuit that carries out communications by inductive coupling between chips to be stacked and mounted via coils formed by on-chip wiring of LSI (Large Scale Integration) chips (refer to Patent Literatures 1 to 11, and Non Patent Literatures 1 to 3).
Particularly, in Patent Literature 10, the present inventors have focused on the point that a rarely used metal wiring layer exists among metal wiring layers in a memory array region, and proposed disposing coils efficiently by forming coils using the conventionally unused metal wiring layer.
FIG. 13A and FIG. 13B are views depicting a configuration of an electronic circuit proposed in Patent Literature 10. FIG. 13A is a plan view, and FIG. 13B is a sectional view taken along a line BB′ of FIG. 13A. The figures depict one LSI chip in an electronic circuit to be stacked and mounted. The LSI chip is composed of a memory array 11, a peripheral circuit 12 being, for example, a decoder, and a peripheral circuit 13 being, for example, a sense amplifier. In the memory array 11, many word lines 14 and bit lines 15 are disposed at a high density, and memory cells 16 are disposed at intersections thereof. The word lines 14 select memory cell lines, and the bit lines 15 write or read out signals. The figure depicts one each of the word lines 14, the bit lines 15, and the memory cells 16. In a region of the memory array 11, a coil 22 connected to a transmitter/receiver 21 and for carrying out communications by inductive coupling is disposed. The coil 22 is formed by a metal wiring layer different from that for the word lines 14 and the bit lines 15. At that time, the shape of the coil 22 is provided as a polygonal shape, here, for example, a square shape, and each side thereof is disposed so as not to be parallel to the word lines 14 and the bit lines 15. This allows minimizing capacitive coupling and magnetic field coupling between the coil 22 and the word lines 14 and bit lines 15.
The figures depict a standard LSI chip having the memory array 11 and a logic circuit 45, for which three metal wiring layers 42 to 44 are stacked upon a semiconductor substrate 41. The metal wiring layer 42 of a first layer forms the word line 14, the metal wiring layer 43 of a second layer forms the bit line 15, and the metal wiring layer 44 of a third layer forms the coil 22. Although three or more metal wiring layers are used for the peripheral circuit 12, 13 and the logic circuit 45, only two layers are mostly used for the memory array 11, and thus an unused metal wiring layer in its region is used to form the coil 22.